1. Field of the Invention
This invention relates generally to a matrix type bus connection system that enables simultaneous operation of master devices connected to a plurality of slave devices, and to a power reduction method of the slave devices.
2. Description of the Related Art
FIG. 2 is a block diagram showing a related matrix type bus connection system.
This matrix type bus connection system includes a plurality of master devices 1i (i=1 to m), a plurality of slave devices 2j (j=1 to n), a matrix type bus circuit 10 for connecting master and slave device arbitrarily.
In principle, the matrix type bus circuit includes a plurality of dedicated buses installed for master devices 1i (each bus is referred to as “master bus” or “bus of master device”) and a plurality of dedicated buses installed for the slave devices 2j (each bus is referred to as “slave bus” or as “bus of the slave device”), the master bus crosses over the slave bus, and controls connection of these buses at the crossing point in accordance with access requests from master devices.
Each master device 1i has a decoder (DEC) 11i and selector (SEL) 12i, provided on each master bus, and each slave device 2j has an arbitration circuit (ARB) 13j and selector 14j, provided on each slave bus.
The decoder 11i specifies a connection target slave device 2j by analyzing an address from master device 1i, and send an access request to the arbitration circuit 13j of the slave device 2j. The arbitration circuit, on the other hand, determines the accessible master device based on the priority of access requests or on the order of the requests from each decoder 11i, and controls the selector 12i and the selector 14j.
The operation of the matrix type bus connection system will now be described below using the case of accessing from master device 11 to the slave device 2n.
The master device 11 issues the target address (addr) of the slave device 2n on the associated master bus. This target address (addr) is read and analyzed by the decoder 111 of the master device 11, and the access request is send from the decoder 111 to an arbitration circuit 13n of the slave device 2n.
When the access request is permitted by the arbitration circuit 13n of the slave device 2n, the arbitration circuit 13n send the selection signal to the selector 14n for connecting the bus of master device 11, and also send the selection signal to selector 121 of master device 11 for connecting the bus of slave device 2n. Thus master device 11 is connected to the slave device 2l.
When the connection is made, the master device 11 issues such information as target address (addr), data transfer type (trans), and transfer count information (burst) to the slave device 2n, the slave device 2n then sends a reply signal (ready) to the master device 11. Thereafter data transfer is executed according to the data transfer type.
In this way, the matrix type bus circuit 10 connects the bus of the master device 1i to the bus of the slave device 2j. Thus the master device 1i can be connected to an arbitrary slave device 2j as long as the target slave device 2j has not yet be connected to other master device 1i.
The similar bus connection system is disclosed in Japanese Patent Kokai (Laid-open Application) Nos. 8-255127 and 10-143444.
However, in the above mentioned matrix type bus connection system, the low-power operation control processing, such as halting to supply clock signal to the slave device 2j, would result in the absence of a reply signal (ready) from the slave device 2j. For this reason, operation of master device is stopped because of the absence of the reply signal from selected slave device 2j.